Electrical characteristics
STM8S105xx
Figure 44: Typical application with I2C bus and timing diagram (1)
VDD
VDD
I²C bus
SDA
SCL
STM8S105xx
SD A
tf(SDA)
S TART
S TART REPEATED
tsu(STA)
S TART
tr(SDA)
tsu(SDA)
th(STA)
tw(SCKL)
th(SDA)
S TOP
tsu(STA:STO)
SCL
tw(SCKH)
tr(SCK)
tf(SCK)
tsu(STO)
ai15385
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
10.3.11
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified.
Table 45: ADC characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
fADC ADC clock frequency
VDDA =2.95 to 5.5 V 1
4
MHz
VDDA =4.5 to 5.5 V 1
6
VDDA Analog supply
VREF+ Positive reference voltage
VREF- Negative reference voltage
VAIN
Conversion voltage range(2)
3
2.75(1)
V SSA
V SSA
5.5 V
VDDA V
0.5(1) V
V DDA V
Devices with
external
VREF+/VREF- pins
VREF-
VREF+ V
CADC Internal sample and hold
capacitor
3
pF
98/127
DocID14771 Rev 9