STM8S105xx
Electrical characteristics
Symbol Parameter
tS (2)
Sampling time
Conditions
fADC = 4 MHz
Min Typ Max Unit
0.75
µs
fADC = 6 MHz
0.5
tSTAB Wakeup time from standby
7
µs
tCONV Total conversion time
fADC = 4 MHz
3.5
µs
(including sampling time,
10-bit resolution)
fADC = 6 MHz
2.33
µs
14
1/fADC
(1) Data guaranteed by design, not tested in production..
(2) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V
Symbol Parameter
Conditions
Typ
Max(1) Unit
|ET|
Total unadjusted error(2)
fADC = 2 MHz
1
2.5
LSB
fADC = 4 MHz
1.4
3
|EO|
Offset error(2)
fADC = 6 MHz
fADC = 2 MHz
1.6
3.5
0.6
2
fADC = 4 MHz
1.1
2.5
|EG|
Gain error(2)
fADC = 6 MHz
fADC = 2 MHz
1.2
2.5
0.2
2
fADC = 4 MHz
0.6
2.5
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