DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.14

21.14.1

Note:

21.14.2

Note:

Watchdog Timer

The Watchdog timer can be used to trigger a reset in the event that the system has

become unresponsive.

Features

Selectable Prescaler - approximately 1 MHz (1 s to 1 s) and approximately 1 KHz (1

ms to 17 min)

• 33 MHz Clock (30 ns Clock Ticks)

• WDT Mode:

— Second stage drives WDT_TOUT high or inverts the previous value. Used only

after first timeout occurs.

— Status bit preserved in RTC well for possible error detection and correction

— Drives WDT_TOUT if OUTPUT is enabled

• Timer can be disabled (default state) or Locked (Hard Reset required to disable

WDT)

• WDT Automatic Reload of Preload value when WDT Reload Sequence is performed

WDT_TOUT is not available as a top-level SoC output.

Use

This Watchdog timer provides a resolution that ranges from 1 s to ~17 minutes. The

timer uses a 35-bit down-counter.

The counter is loaded with the value from the 1st Preload register. The timer is then

enabled and it starts counting down. The time at which the WDT first starts counting

down is called the first stage. If the host fails to reload the WDT before the 35-bit down

counter reaches zero the WDT generates an internal interrupt within the WDT.

After the internal interrupt is generated when the first stage has counted down to zero,

the WDT loads the value from the 2nd Preload register into the WDT's 35-bit Down-

Counter and starts counting down. The WDT is now in the second stage. If the host still

fails to reload the WDT before the second timeout, the WDT drives the WDT_TOUT

signal high and sets the timeout bit (WDT_TIMEOUT). This bit indicates that the

System has become unstable. The WDT_TOUT signal is held high until the system is

Reset or the WDT times out again (Depends on WDT Timeout Configuration). The

process of reloading the WDT involves the following sequence of writes:

• Write 80 to offset WDTBA + 0Ch

• Write 86 to offset WDTBA + 0Ch

• Write 1 to WDT_RELOAD in Reload Register.

The same process is used for setting the values in the preload registers. The only

difference exists in step 3. Instead of writing a '1' to the WDT_RELOAD, you write the

desired preload value into the corresponding Preload register. This value is not loaded

into the 35-bit down counter until the next time the WDT reenters the stage. For

example, if Preload Value 2 is changed, it is not loaded into the 35-bit down counter

until the next time the WDT enters the second stage.

The WDT output, WDT_TOUT, is not available as a top-level SoC output pin

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

911

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