DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.14.3
Figure 55.
Register Map
See Chapter 5.0, “Register Access Methods†for additional information.
Watchdog Timer Register Map
PCI Space
CPU
Core
PCI
CAM
(I/O)
PCI
ECAM
(Mem)
Bus 0
SPI0 F:0
SPI1 F:1
I2C*/GPIO F:2
SDIO/eMMC F:0
HSUART0 F:1
USB Device F:2
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
MAC0 F:6
MAC1 F:7
Host Bridge
D:0,F:0
RP0 F:0
RP0 F:1
Legacy PCI
Header
D:31,F:0
WDTBA
Legacy Bridge
D:31,F:0
Memory
Space
IO Space
WDT IO
Registers
21.14.4 I/O Mapped Registers
Table 136. Summary of I/O Registers—WDTBA
Offset
Start
0h
1h
2h
Offset End
Register ID—Description
0h
“Preload Value 1 Register 0 (PV1R0)—Offset 0h†on page 913
1h
“Preload Value 1 Register 1 (PV1R1)—Offset 1h†on page 913
2h
“Preload Value 1 Register 2 (PV1R2)—Offset 2h†on page 914
Default
Value
FFh
FFh
0Fh
Intel® Quark SoC X1000
DS
912
October 2013
Document Number: 329676-001US
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