DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
Preload Value 1[15:8] (PV1): This register is used to hold the bits 15 down to 8 of
the Preload Value 1 for the Watch Dog Timer. The Value in the Preload Register is
7:0
FFh
RW
Automatically transferred into the 35-bit down counter every time the WDT enters the
first stage. The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based counting (i.e. zero
is counted as part of the decrement).
21.14.4.3 Preload Value 1 Register 2 (PV1R2)—Offset 2h
Access Method
Type: I/O Register
(Size: 8 bits)
PV1R2: [WDTBA] + 2h
WDTBA Type: PCI Configuration Register (Size: 32 bits)
WDTBA Reference: [B:0, D:31, F:0] + 84h
Default: 0Fh
7
4
0
0
0
0
0
1
1
1
1
Bit
Default &
Range Access
Description
7:4
0b
RO
Reserved (RSV): Reserved.
Preload Value 1[19:16] (PV1): This register is used to hold the bits 19 down to 16 of
the Preload Value 1 for the Watch Dog Timer. The Value in the Preload Register is
3:0
Fh
RW
Automatically transferred into the 35-bit down counter every time the WDT enters the
first stage. The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based counting (i.e. zero
is counted as part of the decrement).
21.14.4.4 Preload Value 2 Register 0 (PV2R0)—Offset 4h
Access Method
Type: I/O Register
(Size: 8 bits)
PV2R0: [WDTBA] + 4h
WDTBA Type: PCI Configuration Register (Size: 32 bits)
WDTBA Reference: [B:0, D:31, F:0] + 84h
Default: FFh
7
4
0
1
1
1
1
1
1
1
1
Bit
Default &
Range Access
Description
Preload Value 2[7:0] (PV2): This register is used to hold the bits 7 down to 0 of the
Preload Value 2 for the Watch Dog Timer. The Value in the Preload Register is
7:0
FFh
RW
Automatically transferred into the 35-bit down counter every time the WDT enters the
first stage. The value loaded into the preload register needs to be one less than the
intended period. This is because the timer makes use of zero-based counting (i.e. zero
is counted as part of the decrement).
Intel® Quark SoC X1000
DS
914
October 2013
Document Number: 329676-001US
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