DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Range
2
1
0
Default &
Access
Description
0b
Master/Slave Buffered Mode (MSBM): Not used. Should always be programmed to
WO
0.
0b
WO
Automatic End of Interrupt (AOEI): This bit should normally be programmed to 0.
This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt mode
is programmed.
1b
WO
Microprocessor Mode (MM): This bit must be written to 1 to indicate that the
controller is operating in an Intel Architecture-based system. Writing 0 will result in
undefined behavior.
21.12.3.14 Slave Operational Control Word 1 (SoCW1)—Offset ADh
Access Method
Type: I/O Register
(Size: 8 bits)
SoCW1: ADh
7
4
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
7: 0
Interrupt Request Mask (IRM): When a 1 is written to any bit in this register, the
00h
RW
corresponding IRQ line is masked. When a 0 is written to any bit in this register, the
corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by
the controller. Masking IRQ2 on the master controller will also mask the interrupt
requests from the slave controller.
21.12.3.15 Master Edge/Level Control (ELCR1)—Offset 4D0h
Access Method
Type: I/O Register
(Size: 8 bits)
ELCR1: 4D0h
7
4
0
X
X
X
X
X
0
0
0
Bit
Default &
Range Access
Description
7: 3
2: 0
X
RW
Edge Level Control (ECL[7:3]) (ELC):: In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the interrupt is
recognized by a high level.
0b
RO
RESERVED (RESERVED): Reserved.
21.12.3.16 Slave Edge/Level Control (ELCR2)—Offset 4D1h
Access Method
Type: I/O Register
(Size: 8 bits)
ELCR2: 4D1h
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
901
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