DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

21.13.6

Bit

Default &

Range Access

Description

31: 8

7: 0

0b

RO

RESERVED (RESERVED1): Reserved.

0h

EOI (EOI): When a write is issued to this register, the IOxAPIC will check the lower 8

bits written to this register, and compare it with the vector field for each entry in the I/O

RO

Redirection Table. When a match is found, RTE.RIRR for that entry will be cleared. If

multiple entries have the same vector, each of those entries will have RTE.RIRR cleared.

Index Registers

These registers are selected with the IDX register, and read/written through the WDW

register. Accessing these registers must be done as DW requests, otherwise unspecified

behavior will result. Software should not attempt to write to reserved registers.

Reserved registers may return non-zero values when read.

Note:

There is one pair of redirection (RTE) registers per interrupt line. Each pair forms a 64-

bit RTE register.

Note:

Specified offsets should be placed in IDX, not added to IDX.

Table 135. Index Registers

Offset

00

01

02-0F

10-11

12-13

...

3E-3F

40-FF

Symbol

ID

VS

-

RTE0

RTE1

...

RTE23

-

Register

Identification

Version

Reserved

Redirection Table 0

Redirection Table 1

...

Redirection Table 23

Reserved

21.13.6.1 Identification Register (ID)—Offset 0h

Access Method

Type: Indirect I/O APIC Register

(Size: 32 bits)

Default: 00000000h

ID: 0h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

907

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