DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Table 134. I/O APIC Memory Mapped Registers
Address
FEC00000h
FEC00010h
FEC00040h
Symbol
IDX
WDW
EOI
Register
Index Register
Window Register
End of Interrupt Register
21.13.5.1 Index Register (IDX)—Offset FEC00000h
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
Default: 00h
IDX: FEC00000h
7
4
0
0
0
0
0
0
0
0
0
21.13.5.2
Bit
Default &
Range Access
Description
7: 0
0h
RW
Index (IDX): This 8-bit register selects which indirect register appears in the window
register to be manipulated by software. Software will program this register to select the
desired APIC internal register.
Window Register (WDW)—Offset FEC00010h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Default: FFFFFFFFh
WDW: FEC00010h
31
28
24
20
16
12
8
4
0
11111111111111111111111111111111
21.13.5.3
Bit
Default &
Range Access
Description
31: 0
FFFFFFFFh
RW
Window (WDW): This 32-bit register specifies the data to be read or written to the
register pointed to by the IDX register. This register can be accessed only in DW
quantities.
End of Interrupt Register (EOI)—Offset FEC00040h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Default: 00000000h
EOI: FEC00040h
Intel® Quark SoC X1000
DS
906
October 2013
Document Number: 329676-001US
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