DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

• NMI/INIT: This cannot be delivered while the CPU is in the Stop Grant state. In

addition, this is a break event for power management.

• SMI: There is no way to block the delivery of the SMI#, except through BIOS.

• Virtual Wire Mode B: The Legacy Bridge does not support the INTR of the 8259

routed to the I/OxAPIC pin 0.

21.13.4

Figure 54.

Register Map

See Chapter 5.0, “Register Access Methods” for additional information.

I/O APIC Register Map

Memory

Space

FEC00000h

Index (IDX)

FEC00010h Window (WDW)

FEC00040h End of Int (EOI)

I/O APIC

Space

ID

VS

IDX Value

0h

1h

RTE[0]

RTE[1]

10h, 11h

12h, 13h

RTE[23] 3Eh, 3Fh

21.13.5

Memory Mapped Registers

The APIC is accessed via an indirect addressing scheme. These registers are mapped

into memory space. The registers are shown below.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

905

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