DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
21.13.6.4
Bit
Default &
Range Access
Description
31: 17
16
15
14
13
12
11
10: 8
7: 0
0h
RW
Reserved (RSVD0): Reserved.
1b
Mask (MSK): When set, interrupts are not delivered nor held pending. When cleared,
RW
and edge or level on this interrupt results in the delivery of the interrupt.
0b
Trigger Mode (TM): When cleared, the interrupt is edge sensitive. When set, the
RW
interrupt is level sensitive.
Remote IRR (RIRR): This is used for level triggered interrupts; its meaning is
0b
RW
undefined for edge triggered interrupts. This bit is set when I/O APIC sends the level
interrupt message to the CPU. This bit is cleared when an EOI message is received that
matches the VCT field. This bit is never set for SMI, NMI, INIT, or ExtINT delivery
modes.
0b
Polarity (POL): This specifies the polarity of each interrupt input. When cleared, the
RW
signal is active high. When set, the signal is active low. 0: Active High 1: Active Low
0b
RO
Delivery Status (DS): This field contains the current status of the delivery of this
interrupt. When set, an interrupt is pending and not yet delivered. When cleared, there
is no activity for this entry.
0b
Destination Mode (DSM): This field is used by the local APIC to determine whether it
RW
is the destination of the message.
Delivery Mode (DLM): This field specifies how the APICs listed in the destination field
should act upon reception of this signal. Certain Delivery Modes will only operate as
intended when used in conjunction with a specific trigger mode. These encodings are:
000: Fixed
001: Lowest Priority
0h
010: SMI - Not supported.
RW
011: Reserved
100: NMI - Not supported.
101: INIT - Not supported.
110: Reserved
111: ExtINT
0h
Vector (VCT): This field contains the interrupt vector for this interrupt. Values range
RW
between 10h and FEh.
Redirection Table Entry Upper (RTE[0-23]U)—Offset 11h - 3Fh
Upper 32-bits of the RTE register.
Access Method
Type: Indirect I/O APIC Register
(Size: 32 bits)
Default: 00000000h
RTE[0-23]U: 11h - 3Fh
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Range
31: 24
23: 16
Default &
Access
Description
0h
RW
Destination ID (DID): Destination ID of the local APIC.
0h
RW
Extended Destination ID (EDID): Extended destination ID of the local APIC.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
909
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