DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
7
4
0
X
X
0
X
X
X
X
0
Bit
Default &
Range Access
Description
7: 6
5
4: 1
0
X
RW
Edge Level Control (ECL[15:14]) (ELC1): In edge mode, (bit cleared), the interrupt
is recognized by a low to high transition. In level mode (bit set), the interrupt is
recognized by a high level. Bit 7 applies to IRQ15, and bit 6 to IRQ14.
0b
RO
RESERVED (RESERVED): Reserved.
X
Edge Level Control (ECL[12:9]) (ELC2):: In edge mode, (bit cleared), the interrupt
is recognized by a low to high transition. In level mode (bit set), the interrupt is
RW
recognized by a high level. Bit 4 applies to IRQ12, bit 3 to IRQ11, bit 2 to IRQ10, and bit
1 to IRQ9.
0b
RO
RESERVED (RESERVED): Reserved.
Intel® Quark SoC X1000
DS
902
October 2013
Document Number: 329676-001US
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