DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.13.6.2
Bit
Default &
Range Access
Description
31: 28
27: 24
23: 0
0h
RW
Reserved (RSVD0): Reserved.
0h
RW
APIC Identification (AID): Software must program this value before using the APIC.
0h
RW
Reserved (RSVD1): Reserved.
Version Register (VS)—Offset 1h
Access Method
Type: Indirect I/O APIC Register
(Size: 32 bits)
Default: 00170020h
VS: 1h
31
28
24
20
16
12
8
4
0
00000000000101110000000000100000
21.13.6.3
Bit
Default &
Range Access
Description
31: 24
23: 16
15
14: 8
7: 0
0h
RW
Reserved (RSVD0): Reserved.
17h
RO
Maximum Redirection Entries (MRE): This is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. This field is hardwired to indicate the
total number of interrupts.
0b
Pin Assertion Register Supported (PRQ): The I/O APIC does not implement the Pin
RO
Assertion Register.
0h
RW
Reserved (RSVD1): Reserved.
20h
RO
Version (VS): Identifies the implementation version as I/O APIC.
Redirection Table Entry Lower (RTE[0-23]L)—Offset 10h - 3Eh
Lower 32-bits of the RTE register.
Access Method
Type: Indirect I/O APIC Register
(Size: 32 bits)
Default: 00010000h
RTE[0-23]L: 10h - 3Eh
31
28
24
20
16
12
8
4
0
00000000000000010000000000000000
Intel® Quark SoC X1000
DS
908
October 2013
Document Number: 329676-001US
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