DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.13

I/O APIC

The I/O Advanced Programmable Interrupt Controller (APIC) is used to support line

interrupts more flexibly than the 8259 PIC. Line interrupts are routed to it from

multiple sources, including legacy devices, via the interrupt decoder or they are routed

to it from the interrupt router in the Legacy Bridge. These line-based interrupts are

then used to generate interrupt messages targeting the local APIC in the processor.

21.13.1

Figure 52.

Features

• 24 interrupt lines

— IRQ0-23

• Edge or level trigger mode per interrupt

• Active low or high polarity per interrupt

• Works with local APIC in processor via MSIs

• MSIs can target specific processor core

• Established APIC programming model

Detailed I/O APIC Block Diagram

To/From System Bus

MSI’s

I/O APIC

FEC0 0000h

FEC0 0010h

FEC0 0040h

IDX

WDW

EOI

MSI Machine

INT[0]

ID

VS

RTE[0]

INT[23]

RTE[23]

INT[23:0]

INT0

INT1

INT2

INT3

INT4

INT5

INT6

INT7

INT8

INT9

INT10

INT11

INT12

INT13

INT14

INT15

INT16

INT17

INT18

INT19

INT20

INT21

INT22

INT23

Note: INT13 is unavailable and is effectively tied low within the I/O APIC, INT14 & INT15 are unused in the

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

903

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