DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Figure 53.

SoC and are tied low.

MSIs generated by the I/O APIC are sent as 32-bit memory writes to the Local APIC.

The address and data of the write transaction are used as follows.

MSI Address and Data

RTE[n].DSM Destination Mode

Set if RTE[n].DLM = 001b Redirection Hint

RTE[n].EDID Extended Dest. ID

RTE[n].DID Destination ID

FEEh

MSI

Address

31 : 20

MSI

Data

31:16

19 : 12

11 : 4

00b

3 2 1:0

151413:1211 10:8

7:0

0000h

00b

RTE[n].TM Trigger Mode

Delivery Status (1b)

RTE[n].DSM Destination Mode

RTE[n].DLM Delivery Mode

RTE[n].VCT Vector

21.13.2

21.13.3

Destination ID (DID) and Extended Destination ID (EDID) are used to target a specific

processor core’s local APIC.

Use

The I/O APIC contains indirectly accessed I/O APIC registers and normal memory

mapped registers. There are three memory mapped registers:

• Index Register (IDX)

• Window Register (WDW)

• End Of Interrupt Register (EOI)

The Index register selects an indirect I/O APIC register (ID/VS/RTE[n]) to appear in the

Window register.

The Window register is used to read or write the indirect register selected by the Index

register.

The EOI register is written to by the Local APIC in the processor. The I/O APIC

compares the lower eight bits written to the EOI register to the Vector set for each

interrupt (RTE.VCT). All interrupts that match this vector will have their RTE.RIRR

register cleared. All other EOI register bits are ignored.

Unsupported Modes

These delivery modes are not supported for the following reasons:

Intel® Quark SoC X1000

DS

904

October 2013

Document Number: 329676-001US

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