DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Figure 51. 8259 Register Map

PCI Space

CPU

Core

PCI

CAM

(I/O)

PCI

ECAM

(Mem)

Bus 0

SPI0 F:0

SPI1 F:1

I2C*/GPIO F:2

SDIO/eMMC F:0

HSUART0 F:1

USB Device F:2

EHCI Host F:3

OCHI Host F:4

HSUART1 F:5

MAC0 F:6

MAC1 F:7

Host Bridge

D:0,F:0

RP0 F:0

RP0 F:1

Legacy PCI

Header

D:31,F:0

Legacy Bridge

D:31,F:0

Memory

Space

IO Space

Fixed IO

Registers

21.12.3

Note:

I/O Registers

The interrupt controller registers are located at 20h and 21h for the master controller

(IRQ0-7), and at A0h and A1h for the slave controller (IRQ8-13). These registers have

multiple functions, depending upon the data written to them. Table 132 describes the

different register possibilities for each address.

The register descriptions after Table 132 represent one register possibility.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

891

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