DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Bit

Range

2

1

0

Default &

Access

Description

0b

Master/Slave in Buffered Mode (MSBM): Not used. Should always be programmed

WO

to 0.

0b

WO

Automatic End of Interrupt (AOEI): This bit should normally be programmed to 0.

This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt mode

is programmed.

1b

WO

Microprocessor Mode (MM): This bit must be written to 1 to indicate that the

controller is operating in an Intel Architecture-based system. Writing 0 will result in

undefined behavior.

21.12.3.7 Master Operational Control Word 1 (MOCW1)—Offset 2Dh

Access Method

Type: I/O Register

(Size: 8 bits)

MOCW1: 2Dh

7

4

0

0

0

0

0

0

0

0

0

21.12.3.8

Bit

Default &

Range Access

Description

7: 0

Interrupt Request Mask (IRM): When a 1 is written to any bit in this register, the

00h

RW

corresponding IRQ line is masked. When a 0 is written to any bit in this register, the

corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by

the controller. Masking IRQ2 on the master controller will also mask the interrupt

requests from the slave controller.

Slave Initialization Command Word 1 (SICW1)—Offset A0h

.A write to Initialization Command Word 1 starts the interrupt controller initialization

sequence, during which the following occurs:

• The Interrupt Mask register is cleared.

• IRQ7 input is assigned priority 7.

• The slave mode address is set to 7.

• Special Mask Mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to

complete the initialization sequence.

Access Method

Type: I/O Register

(Size: 8 bits)

SICW1: A0h

7

4

0

X

X

X

X

X

X

X

X

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

897

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