DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Type: I/O Register
(Size: 8 bits)
MOCW2: 24h
7
4
0
0
0
1
X
X
X
X
X
21.12.3.4
Bit
Default &
Range Access
Description
7: 5
4: 3
2: 0
001b
WO
X
WO
X
WO
Rotate and EOI Codes (REOI): R, SL, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A chart of these combinations is
listed above under the bit definition.
000 - Rotate in Auto EOI Mode (Clear)
001 - Non-specific EOI command
010 - No Operation
011 - *Specific EOI Command
100 - Rotate in Auto EOI Mode (Set)
101 - Rotate on Non-Specific EOI Command
110 - *Set Priority Command
111 - *Rotate on Specific EOI Command
*L0 - L2 Are Used
OCW2 Select (OCW2S): When selecting OCW2, bits 4:3 = 00
Interrupt Level Select (L2, L1, L0) (ILS): L2, L1, and L0 determine the interrupt
level acted upon when the SL bit is active. A simple binary code, outlined above, selects
the channel for the command to act upon. When the SL bit is inactive, these bits do not
have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.
Bits Interrupt Level Bits Interrupt Level
000 IRQ0/8
100 IRQ4/12
001 IRQ1/9
101 IRQ5/13
010 IRQ2/10 110 IRQ6/14
011 IRQ3/11 111 IRQ7/15
Master Initialization Command Word 3 (MICW3)—Offset 25h
Access Method
Type: I/O Register
(Size: 8 bits)
MICW3: 25h
7
4
0
X
X
X
X
X
X
X
X
21.12.3.5
Bit
Default &
Range Access
Description
7: 3
2
1: 0
X
WO
MBZ (MBZ): These bits must be programmed to zero.
X
Cascaded Controller Connection (CCC): This bit must always be programmed to a 1
WO
to indicate the slave controller for interrupts 8 15 is cascaded on IRQ2.
X
WO
MBZ (MBZ1): These bits must be programmed to zero.
Master Operational Control Word 3 (MOCW3)—Offset 28h
Access Method
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
895
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