DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Table 132. 8259 I/O Registers Alias Locations

Registers

Original I/O Location

MICW1

MOCW2

20h

MOCW3

MICW2

MICW3

21h

MICW4

MOCW1

SICW1

SoCW2

SoCW3

A0h

SICW2

SICW3

SICW4

SoCW1

ELCR1

ELCR2

A1h

4D0h

4D1h

Alias I/O Locations

24h

28h

2Ch

30h

34h

38h

3Ch

25h

29h

2Dh

31h

35h

39h

3Dh

A4h

A8h

ACh

B0h

B4h

B8h

BCh

A5h

A9h

ADh

B1h

B5h

B9h

BDh

N/A

N/A

Table 133. Summary of I/O Registers

Offset

Start

20h

21h

24h

Offset

End

20h

21h

24h

Register ID—Description

“Master Initialization Command Word 1 (MICW1)—Offset 20h” on

page 893

“Master Initialization Command Word 2 (MICW2)—Offset 21h” on

page 894

“Master Operational Control Word 2 (MOCW2)—Offset 24h” on

page 894

Default

Value

81Fh

63h

67h

Intel® Quark SoC X1000

DS

892

October 2013

Document Number: 329676-001US

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