DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.10.5.1 Offset 0Ah: Register A

This register is in the RTC well, and is used for general configuration of the RTC

functions.

Access Method

Type: RTC Indexed Register

(Size: 8 bits)

Default: xxxxxxxxb

7

4

x

xxx

0

xxxx

Bit

Range

7

Default &

Access

Description

xb

RW

Update in progress (UIP): When set, an update is in progress. When cleared, the

update cycle will not start for at least 488 µs. The time, calendar, and alarm information

in RAM is always available when this bit is cleared.

Division Chain Select: Controls the divider chain for the oscillator; not affected by

RSMRST# or any other reset signal.

6: 4

000b: Invalid

xb

RW

001b: Invalid

010b: Normal Operation

011b: Bypass 5 Stages (Test Mode Only)

100b: Bypass 10 Stages (Test Mode Only)

101b: Bypass 15 Stages (Test Mode Only)

110b: Divider Reset

111b: Divider Reset

Rate Select: Selects one of 13 taps of the 15 stage divider chain. The selected tap can

generate a periodic interrupt when B.PIE bit is set. Otherwise this tap sets C.PF.

3: 0

0000b: Interrupt Never Toggles

0001b: 3.90625 ms

0010b: 7.8125 ms

0011b: 122.070 μs

0100b: 244.141 μs

xb

0101b: 488.281 μs

0110b: 976.5625 μs

RW

0111b: 1.953125 ms

1000b: 3.90625 ms

1001b: 7.8125 ms

1010b: 15.625 ms

1011b: 31.25 ms

1100b: 62.5 ms

1101b: 125 ms

1110b: 250 ms

1111b: 500 ms

21.10.5.2 Offset 0Bh: Register B - General Configuration

This register resides in the resume well.

Access Method

Type: RTC Indexed Register

(Size: 8 bits)

Default: x0x00xxxb

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

881

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