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DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH
Intel
Intel 
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
21.12.1
Features
In addition to providing support for ISA compatible interrupts, this interrupt controller
can also support PCI based interrupts (PIRQs) by mapping the PCI interrupt onto a
compatible ISA interrupt line. Each 8259 controller supports eight interrupts, numbered
0–7. Table 129 shows how the controllers are connected.
Note:
The SoC does not implement any external PIRQ# signals. The PIRQs referred to in this
section originate from the interrupt routing unit.
Table 129. Interrupt Controller Connections
8259
Master
Slave
8259
Input
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Connected Pin / Function
Internal Timer / Counter 0 output or HPET Timer #0
Reserved
Slave controller INTR output
IRQ3 via PIRQx
IRQ4 via PIRQx
IRQ5 via PIRQx
IRQ6 via PIRQx
IRQ7 via PIRQx
Inverted IRQ8# from internal RTC or HPET Timer #1
IRQ9 via SCI or PIRQx
IRQ10 via SCI or PIRQx
IRQ11 via SCI or PIRQx or HPET Timer #2
IRQ12 via PIRQx
Reserved
IRQ14 via PIRQx
IRQ15 via PIRQx
The SoC cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
SoC PIC.
Interrupts can be programmed individually to be edge or level, except for IRQ0, IRQ2
and IRQ8#.
Note:
Active-low interrupt sources (such as a PIRQ#) are inverted inside the SoC. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
21.12.1.1 Interrupt Handling
21.12.1.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. Table 130 defines the IRR, ISR, and IMR.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
885

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