DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.11.1.1.1 For Consumption by the Interrupt Router

When a PCI-mapped device in the SoC asserts or de-asserts an INT[A:D] interrupt, an

interrupt message is sent to the decoder. This message is decoded to indicate to the

interrupt router which specific interrupt is asserted or de-asserted and which device the

INT[A:D] interrupt originated from.

21.11.1.1.2 For Consumption by the 8259 PIC

When a device in the SoC asserts or deasserts a legacy interrupt (IRQ), an interrupt

message is sent to the decoder. This message is decoded to indicate to the 8259 PIC

which specific interrupt (IRQ[3, 4, 5, 6, 7, 13, 14 or 15]) was asserted or deasserted.

21.11.1.2 Interrupt Router

The interrupt router aggregates the INT[A:D] interrupts for each PCI-mapped device in

the SoC, received from the interrupt decoder. It then maps these aggregated interrupts

to 8 PCI-based interrupts: PIRQ[A:H]. This mapping is configured using the 4 Interrupt

Queue Agent Registers: IRQAGENT0, IRQAGENT1, IRQAGENT2 and IRQAGENT3.

Table 128. IRQAGENT Description

IRQAGENT

0

1

2

3

Description

Remote Management Unit

PCIe*

D:23

Reserved

IO Fabric

D:20 & D21

Single-Function/ Multi-Function

Single-Function (Supports INTA only)

Multi-Function (Supports INTA, INTB, INTC & INTD)

Single-Function (Supports INTA only)

Multi-Function (Supports INTA, INTB, INTC & INTD)

PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259

PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control

Registers: PIRQA, PIQRB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH.

When the PCI based interrupts are consumed by the IO-APIC, a fixed routing scheme is

used where interrupts PIRQ[A:H] are routed to IO-APIC interrupts IRQ[16:23].

21.11.1.2.1 Routing PCI Based Interrupts to 8259 PIC

The interrupt router can be programmed to allow PIRQA-PIRQH to be routed internally

to the 8259 as ISA compatible interrupts IRQ 3–7, 9–12 & 14–15. The assignment is

programmable through the 8 PIRQx Routing Control Registers: PIRQA, PIQRB, PIRQC,

PIRQD, PIRQE, PIRQF, PIRQG, PIRQH. See Section 21.3 for register details. One or

more PIRQs can be routed to the same IRQ input. If ISA Compatible Interrupts are not

required, the Route registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive. When a PIRQx# is routed to

specified IRQ line, software must change the IRQ's corresponding ELCR bit to level

sensitive mode. The SoC internally inverts the PIRQx# line to send an active high level

to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer

be used by an active high device (through SERIRQ). However, active low interrupts can

share their interrupt with PCI interrupts.

21.12

8259 Programmable Interrupt Controllers (PIC)

The SoC provides an ISA-compatible programmable interrupt controller (PIC) that

incorporates the functionality of two, cascaded 8259 interrupt controllers.

Intel® Quark SoC X1000

DS

884

October 2013

Document Number: 329676-001US

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