DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Range
3: 0
Default &
Access
0b
RO
Reserved (RSV1)
Description
21.10.5.4 Offset 0Dh: Register D - Flag Register
Access Method
Type: RTC Indexed Register
(Size: 8 bits)
Default: 1xxxxxxxb
7
4
0
1
x
xxxxxx
21.10.6
Bit
Range
7
6
5: 0
Default &
Access
Description
0b
Valid RAM and Time Bit (VRT): This bit should always be written as a 0 for write
RC
cycle, however it will return a 1 for read cycles.
0b
RC
Reserved (RSV1): This bit always returns a 0 and should be set to 0 for write cycles.
xb
Date Alarm (DA): These bits store the date of month alarm value. If set to 000000,
then a don’t care state is assumed. If the date alarm is not enabled, these bits will
RC
return zeros to mimic the functionality of the Motorola 146818B. These bits are not
affected by any reset assertion.
References
Accessing the Real Time Clock Registers and the NMI Enable Bit:
ftp://download.intel.com/design/intarch/PAPERS/321088.pdf
21.11
Interrupt Decoding & Routing
The Legacy Bridge provides registers that are used to decode and route interrupts
received from devices within the SoC.
The interrupt decoder is responsible for receiving interrupt messages from other
devices in the SoC and decoding them for consumption by the interrupt router, the
8259 PICs and/or the I/O APIC.
The interrupt router is responsible for mapping each incoming interrupt to the
appropriate PIRQx, for consumption by the 8259 PICs and/or I/O APIC.
21.11.1 Features
21.11.1.1 Interrupt Decoder
The interrupt decoder receives interrupt messages from devices in the SoC. These
interrupts can be split into two primary groups:
• For consumption by the interrupt router
• For consumption by the 8259 PIC
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
883
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