DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the

interrupt vector. If no interrupt request is present because the request was too

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of

the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate

EOI command is issued at the end of the interrupt subroutine.

21.12.1.2 Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. This is a four byte sequence

to ICW1, ICW2, ICW3 and ICW4. The four initialization command words are referred to

by their acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the I/

O memory space: 20h for the master controller, and A0h for the slave controller.

21.12.1.2.1 ICW1

A write to the master or slave controller base address with data bit 4 equal to 1 is

interpreted as a write to ICW1. Upon sensing this write, the PIC expects three more

byte writes to 21h for the master controller, or A1h for the slave controller, to complete

the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following

automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high

transition to generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special mask mode is cleared and Status Read is set to IRR.

21.12.1.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the

interrupt vector that will be released during an interrupt acknowledge. A different base

is selected for each interrupt controller.

21.12.1.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to

cascade the slave controller. Within the SoC, IRQ2 is used. Therefore, MICW3.CCC

is set to a 1, and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master

controller broadcasts a code to the slave controller if the cascaded interrupt won

arbitration on the master controller. The slave controller compares this

identification code to the value stored in its ICW3, and if it matches, the slave

controller assumes responsibility for broadcasting the interrupt vector.

21.12.1.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At

the very least, ICW4.MM must be set to a 1 to indicate that the controllers are

operating in an Intel Architecture-based system.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

887

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