DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
7
4
0
x
0
x
0
0
x
x
x
Bit
Default &
Range Access
Description
7
xb
RW
Set Clock (SET): When cleared, an update cycle occurs once each second. If set, a
current update cycle will abort and subsequent update cycles will not occur until SET is
returned to zero. When set, SW may initialize time and calendar bytes safely.
6
0b
Periodic Interrupt Enable (PIE): When set, and C.PF is set, an interrupt is
RW
generated.
5
xb
RW
Alarm Interrupt Enable (AIE): When set, and C.AF is set, an interrupt is generated.
4
0b
Update-ended Interrupt Enable (UIE): When set and C.UF is set, an interrupt is
RW
generated.
3
0b
RW
Square Wave Enable (SQWE): Not implemented.
2
xb
Data Mode (DM): When set, represents binary representation. When cleared, denotes
RW
BCD.
1
xb
RW
Hour Format (HF): When set, twenty-four hour mode is selected. When cleared,
twelve-hour mode is selected. In twelve hour mode, the seventh bit represents AM
(cleared) and PM (set).
0
xb
RW
Daylight Savings Enable (DSE): Not implemented
21.10.5.3 Offset 0Ch: Register C - Flag Register
All bits in this register are cleared when this register is read.
Access Method
Type: RTC Indexed Register
(Size: 8 bits)
Default: 00x00000b
7
4
0
0
x
0
0
0000
Bit
Default &
Range Access
Description
7
0b
Interrupt Request Flag (IRQF): This bit is an AND of the flag with its corresponding
RC
interrupt enable in register B, and causes the RTC Interrupt to be asserted.
6
0b
RC
Periodic Interrupt Flag (PF): Set when the tap as specified by A.RS is one.
5
xb
RC
Alarm Flag (AF): Set after all Alarm values match the current time.
4
0b
RC
Update-ended Flag (UF): Set immediately following an update cycle for each second.
Intel® Quark SoC X1000
DS
882
October 2013
Document Number: 329676-001US
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