DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Table 130. Interrupt Status Registers

Bit

Description

IRR

Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge

mode, and by an active high level in level mode.

ISR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an

interrupt acknowledge cycle is seen, and the vector returned is for that interrupt.

IMR

Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts

will not generate INTR.

21.12.1.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated into a

Interrupt Acknowledge Cycle by the SoC. The PIC translates this command into two

internal INTA# pulses expected by the 8259 controllers. The PIC uses the first internal

INTA# pulse to freeze the state of the interrupts for priority resolution. On the second

INTA# pulse, the master or slave sends the interrupt vector to the processor with the

acknowledged interrupt code. This code is based upon the ICW2.IVBA bits, combined

with the ICW2.IRL bits representing the interrupt within that controller.

Note:

References to ICWx and OCWx registers are relevant to both the master and slave

8259 controllers.

Table 131. Content of Interrupt Vector Byte

Master, Slave Interrupt

IRQ7,15

IRQ6,14

IRQ5,13

IRQ4,12

IRQ3,11

IRQ2,10

IRQ1,9

IRQ0,8

Bits [7:3]

ICW2.IVBA

Bits [2:0]

111

110

101

100

011

010

001

000

21.12.1.1.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge

cycle.

4. Upon observing the special cycle, the SoC converts it into the two cycles that the

internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge

pulse on the internal INTA# pin of the cascaded interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first

pulse, a slave identification code is broadcast by the master to the slave on a

private, internal three bit wide bus. The slave controller uses these bits to

determine if it must respond with an interrupt vector during the second INTA#

pulse.

Intel® Quark SoC X1000

DS

886

October 2013

Document Number: 329676-001US

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