DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

Table 136. Summary of I/O Registers—WDTBA (Continued)

Offset

Start

4h

5h

6h

Ch

Dh

10h

18h

Offset End

Register ID—Description

4h

“Preload Value 2 Register 0 (PV2R0)—Offset 4h” on page 914

5h

“Preload Value 2 Register 1 (PV2R1)—Offset 5h” on page 915

6h

“Preload Value 2 Register 2 (PV2R2)—Offset 6h” on page 915

Ch

“Reload Register 0 (RR0)—Offset Ch” on page 915

Dh

“Reload Register 1 (RR1)—Offset Dh” on page 916

10h

“WDT Configuration Register (WDTCR)—Offset 10h” on page 916

18h

“WDT Lock Register (WDTLR)—Offset 18h” on page 917

Default

Value

FFh

FFh

0Fh

00h

00h

00h

00h

21.14.4.1 Preload Value 1 Register 0 (PV1R0)—Offset 0h

Access Method

Type: I/O Register

(Size: 8 bits)

PV1R0: [WDTBA] + 0h

WDTBA Type: PCI Configuration Register (Size: 32 bits)

WDTBA Reference: [B:0, D:31, F:0] + 84h

Default: FFh

7

4

0

1

1

1

1

1

1

1

1

Bit

Default &

Range Access

Description

Preload Value 1[7:0] (PV1): This register is used to hold the bits 7 down to 0 of the

Preload Value 1 for the Watch Dog Timer. The Value in the Preload Register is

7:0

FFh

RW

Automatically transferred into the 35-bit down counter every time the WDT enters the

first stage. The value loaded into the preload register needs to be one less than the

intended period. This is because the timer makes use of zero-based counting (i.e. zero

is counted as part of the decrement).

21.14.4.2 Preload Value 1 Register 1 (PV1R1)—Offset 1h

Access Method

Type: I/O Register

(Size: 8 bits)

PV1R1: [WDTBA] + 1h

WDTBA Type: PCI Configuration Register (Size: 32 bits)

WDTBA Reference: [B:0, D:31, F:0] + 84h

Default: FFh

7

4

0

1

1

1

1

1

1

1

1

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

913

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