DSPIC33FJ16GS102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ16GS102-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

REGISTER 19-1: ADCON: A/D CONTROL REGISTER (CONTINUED)

bit 4

bit 3

bit 2-0

ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1)

1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger

pulse is detected.

0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling

process in two ADC clock cycles.

Unimplemented: Read as ‘0’

ADCS<2:0>: A/D Conversion Clock Divider Select bits(1)

111 = FADC/8

110 = FADC/7

101 = FADC/6

100 = FADC/5

011 = FADC/4 (default)

010 = FADC/3

001 = FADC/2

000 = FADC/1

Note 1: This control bit can only be changed while ADC is disabled (ADON = 0), and only applies to single SAR

devices.

DS70318D-page 246

Preliminary

© 2009 Microchip Technology Inc.

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