dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-3: ADBASE: A/D BASE REGISTER(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
ADBASE<15:8>
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
ADBASE<7:1>
R/W-0
R/W-0
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-1
bit 0
ADBASE<15:1>: This register contains the base address of the user’s ADC Interrupt Service Routine
jump table. This register, when read, contains the sum of the ADBASE register contents and the
encoded value of the PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the
highest priority, and P6RDY is the lowest priority.
Unimplemented: Read as ‘0’
Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero.
2: As an alternative to using the ADBASE Register, the ADCP0-6 ADC Pair Conversion Complete Interrupts
can be used to invoke A to D conversion completion routines for individual ADC input pairs.
REGISTER 19-4: ADPCFG: A/D PORT CONFIGURATION REGISTER
U-0
—
bit 15
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
PCFG11
PCFG10
R/W-0
PCFG9
R/W-0
PCFG8
bit 8
R/W-0
PCFG7
bit 7
R/W-0
PCFG6
R/W-0
PCFG5
R/W-0
PCFG4
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
PCFG<11:0>: A/D Port Configuration Control bits(1,2,3,4)
1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS
0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage
Note: Not all PCFGx bits are available on all devices. See Figure 19-1 through Figure 19-6 for the available
analog pins (PCFGx = ANx, where x = 0-11).
DS70318D-page 248
Preliminary
© 2009 Microchip Technology Inc.