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DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

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Description
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DSPIC33EV64GM102-I/SO Datasheet PDF : 500 Pages
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TABLE 4-19: NVM REGISTER MAP
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
NVMCON
0728 WR WREN WRERR NVMSIDL —
NVMADR
072A
NVMADRU
072C —
NVMKEY
072E —
NVMSRCADRL 0730
NVMSRCADRH 0732 —
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
RPDF
Bit 8
Bit 7
Bit 6
URERR
NVMADR<15:0>
NVMSRCADR<15:1>
Bit 5
Bit 4
Bit 3
Bit 2
NVMOP3 NVMOP2
NVMADRU<23:16>
NVMKEY<7:0>
NVMSRCADR<23:16>
Bit 1
Bit 0
All
Resets
NVMOP1 NVMOP0 0000
0000
0000
0000
0
0000
0000
TABLE 4-20: SYSTEM CONTROL REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON 0740 TRAPR IOPUWR —
— VREGSF
CM
OSCCON 0742 —
COSC2 COSC1 COSC0 —
NOSC2 NOSC1
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1
PLLFBD 0746 —
OSCTUN 0748 —
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on the Configuration fuses.
VREGS
NOSC0
FRCDIV0
EXTR
SWR SWDTEN WDTO SLEEP IDLE
BOR
POR Note 1
CLKLOCK IOLOCK LOCK
CF
OSWEN Note 2
PLLPOST1 PLLPOST0
— PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 0000
PLLDIV<8:0>
0000
TUN<5:0>
0000
TABLE 4-21: REFERENCE CLOCK REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
REFOCON 074E ROON
ROSSLP ROSEL RODIV3 RODIV2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
RODIV1
Bit 8
RODIV0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000

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