4.3 Special Function Register Maps
TABLE 4-1: CPU CORE REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
W0
0000
W0 (WREG)
W1
0002
W1
W2
0004
W2
W3
0006
W3
W4
0008
W4
W5
000A
W5
W6
000C
W6
W7
000E
W7
W8
0010
W8
W9
0012
W9
W10
0014
W10
W11
0016
W11
W12
0018
W12
W13
001A
W13
W14
001C
W14
W15
001E
W15
SPLIM
0020
SPLIM
ACCAL
0022
ACCAL
ACCAH
0024
ACCAH
ACCAU
0026
Sign Extension of ACCA<39>
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
Sign Extension of ACCB<39>
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
—
DSRPAG 0032
—
—
—
—
—
—
DSWPAG 0034
—
—
—
—
—
—
—
RCOUNT 0036
REPEAT Loop Counter Register
DCOUNT 0038
DCOUNT<15:1>
DOSTARTL 003A
DOSTARTL<15:1>
DOSTARTH 003C —
—
—
—
—
—
—
—
—
DOENDL 003E
DOENDL<15:1>
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ACCAU
ACCBU
Program Counter High Word Register
Data Space Read Page Register
Data Space Write Page Register
—
DOSTARTH<5:0>
Bit 0
—
0
0
0
—
All
Reset
s
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0001
0001
xxxx
xxxx
xxxx
00xx
xxxx