TABLE 4-5: UART1 AND UART2 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
U1MODE 0220 UARTEN
—
USIDL
IREN RTSMD —
UEN1 UEN0 WAKE
LPBACK ABAUD URXINV BRGH
U1STA
0222 UTXISEL1 UTXINV UTXISEL0
—
UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
U1TXREG 0224
—
—
—
—
—
—
—
UART1 Transmit Register
U1RXREG 0226
—
—
—
—
—
—
—
UART1 Receive Register
U1BRG
0228
UART1 Baud Rate Generator Prescaler Register
U2MODE 0230 UARTEN
—
USIDL
IREN RTSMD —
UEN1 UEN0 WAKE
LPBACK ABAUD URXINV BRGH
U2STA
0232 UTXISEL1 UTXINV UTXISEL0
—
UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
U2TXREG 0234
—
—
—
—
—
—
—
UART2 Transmit Register
U2RXREG 0236
—
—
—
—
—
—
—
UART2 Receive Register
U2BRG
0238
UART2 Baud Rate Generator Prescaler Register
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 2
PDSEL1
FERR
PDSEL1
FERR
Bit 1
PDSEL0
OERR
PDSEL0
OERR
Bit 0
All
Resets
STSEL 0000
URXDA 0110
xxxx
0000
STSEL
URXDA
0000
0000
0110
xxxx
0000
0000
TABLE 4-6: SPI1 AND SPI2 REGISTER MAP
SFR
Name
Addr. Bit 15 Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
SPI1STAT 0240 SPIEN
—
SPISIDL
—
—
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT
SPI1CON1 0242 —
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN CKP MSTEN
SPI1CON2 0244 FRMEN SPIFSD FRMPOL —
—
—
—
—
—
—
—
SPI1BUF 0248
SPI1 Transmit and Receive Buffer Register
SPI2STAT 0260 SPIEN
—
SPISIDL
—
—
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT
SPI2CON1 0262 —
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN CKP MSTEN
SPI2CON2 0264 FRMEN SPIFSD FRMPOL —
—
—
—
—
—
—
—
SPI2BUF 0268
SPI2 Transmit and Receive Buffer Register
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SISEL2
SPRE2
—
SISEL2
SPRE2
—
Bit 3
SISEL1
SPRE1
—
SISEL1
SPRE1
—
Bit 2
SISEL0
SPRE0
—
SISEL0
SPRE0
—
Bit 1
Bit 0
All
Resets
SPITBF SPIRBF
PPRE1 PPRE0
FRMDLY SPIBEN
0000
0000
0000
SPITBF SPIRBF
PPRE1 PPRE0
FRMDLY SPIBEN
0000
0000
0000
0000
0000