DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

TABLE 4-26: DMAC REGISTER MAP (CONTINUED)

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

DMALCA

0BF6 —

—

—

—

—

—

—

—

—

—

—

—

DSADRL

0BF8

DSADR<15:0>

DSADRH

0BFA —

—

—

—

—

—

—

—

DSADR<23:16>

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

LSTCH<3:0>

000F

0000

0000

TABLE 4-27: PWM REGISTER MAP

SFR

Name

Addr.

Bit 15

Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

PTCON 0C00 PTEN

— PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0

PTCON2 0C02

—

—

—

—

——

—

—

—

—

—

—

—

PCLKDIV<2:0>

PTPER 0C04

PTPER<15:0>

SEVTCMP 0C06

SEVTCMP<15:0>

MDC

0C0A

MDC<15:0>

CHOP 0C1A CHPCLKEN —

—

—

— — CHOPCLK9 CHOPCLK8 CHOPCLK7 CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0

PWMKEY 0C1E

PWMKEY<15:0>

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

0000

0000

FFF8

0000

0000

0000

0000

TABLE 4-28: PWM GENERATOR 1 REGISTER MAP

SFR

Name

Addr. Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN

TRGIEN

ITB

MDCS

DTC1 DTC0

DTCP

—

—

CAM

XPRES

IUE

IOCON1 0C22 PENH PENL POLH POLL

PMOD1

PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0

SWAP

OSYNC

FCLCON1 0C24 — CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0

CLPOL

CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0

PDC1

0C26

PDC1<15:0>

PHASE1 0C28

PHASE1<15:0>

DTR1

0C2A —

—

DTR1<13:0>

ALTDTR1 0C2C —

—

ALTDTR1<13:0>

TRIG1

0C32

TRGCMP<15:0>

TRGCON1 0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0

—

—

—

—

—

— TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0

PWMCAP1 0C38

PWMCAP1<15:0>

LEBCON1 0C3A PHR

PHF

PLR

PLF FLTLEBEN CLLEBEN

—

—

—

—

BCH

BCL

BPHH

BPHL

BPLH

BPLL

LEBDLY1 0C3C —

—

—

—

LEB<11:0>

AUXCON1 0C3E —

—

—

— BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 —

— CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

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