ST72P623 View Datasheet(PDF) - STMicroelectronics

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Description

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ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.7 Parity Control

even number of “1s” if even parity is selected

Parity control (generation of parity bit in transmis-

sion and parity checking in reception) can be ena-

bled by setting the PCE bit in the SCICR1 register.

Depending on the frame length defined by the M

(PS = 0) or an odd number of “1s” if odd parity is

selected (PS = 1). If the parity check fails, the PE

flag is set in the SCISR register and an interrupt is

generated if PIE is set in the SCICR1 register.

bit, the possible SCI frame formats are as listed in 10.5.4.8 SCI Clock Tolerance

Table 20.

During reception, each bit is sampled 16 times.

Table 20. Frame Formats

The majority of the 8th, 9th and 10th samples is

considered as the bit value. For a valid bit detec-

M bit PCE bit

SCI frame

tion, all the three samples should have the same

0

0

| SB | 8 bit data | STB |

) 0

1

| SB | 7-bit data | PB | STB |

t(s 1

0

| SB | 9-bit data | STB |

1

1

| SB | 8-bit data PB | STB |

uc Legend: SB = Start Bit, STB = Stop Bit,

d PB = Parity Bit

ro Note: In case of wake up by an address mark, the

P MSB bit of the data is taken into account and not

the parity bit

te Even parity: the parity bit is calculated to obtain

le an even number of “1s” inside the frame made of

o the 7 or 8 LSB bits (depending on whether M is

s equal to 0 or 1) and the parity bit.

Ob Example: data = 00110101; 4 bits set => parity bit

- is 0 if even parity is selected (PS bit = 0).

) Odd parity: the parity bit is calculated to obtain an

t(s odd number of “1s” inside the frame made of the 7

or 8 LSB bits (depending on whether M is equal to

c 0 or 1) and the parity bit.

du Example: data = 00110101; 4 bits set => parity bit

ro is 1 if odd parity is selected (PS bit = 1).

P Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

te not transmitted but is changed by the parity bit.

le Reception mode: If the PCE bit is set then the in-

Obso terface checks if the received data byte has an

value otherwise the noise flag (NF) is set. For ex-

ample: If the 8th, 9th and 10th samples are 0, 1

and 1 respectively, then the bit value is “1”, but the

Noise Flag bit is set because the three samples

values are not the same.

Consequently, the bit length must be long enough

so that the 8th, 9th and 10th samples have the de-

sired bit value. This means the clock frequency

should not vary more than 6/16 (37.5%) within one

bit. The sampling clock is resynchronized at each

start bit, so that when receiving 10 bits (one start

bit, 1 data byte, 1 stop bit), the clock deviation

must not exceed 3.75%.

Note: The internal sampling clock of the microcon-

troller samples the pin value on every falling edge.

Therefore, the internal sampling clock and the time

the application expects the sampling to take place

may be out of sync. For example: If the baud rate

is 15.625 Kbaud (bit length is 64µs), then the 8th,

9th and 10th samples are at 28µs, 32µs and 36µs

respectively (the first sample starting ideally at

0µs). But if the falling edge of the internal clock oc-

curs just before the pin value changes, the sam-

ples would then be out of sync by ~4us. This

means the entire bit length must be at least 40µs

(36µs for the 10th sample + 4µs for synchroniza-

tion with the internal sampling clock).

74/139

Doc ID 6996 Rev 5

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