ST72P623 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72P623
STMicroelectronics
ST72P623 Datasheet PDF : 139 Pages
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
7
0
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
TR dividing factor
1
2
SCT2
0
0
SCT1
0
0
SCT0
0
1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
4
0
1
0
) The Data register performs a double function (read
t(s and write) since it is composed of two registers,
c one for transmission (TDR) and one for reception
u (RDR).
d The TDR register provides the parallel interface
ro between the internal bus and the output shift reg-
ister (see Figure 46).
P The RDR register provides the parallel interface
te between the input shift register and the internal
le bus (see Figure 46).
so BAUD RATE REGISTER (SCIBRR)
b Read/Write
- O Reset Value: 0000 0000 (00h)
t(s) 7
0
c SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
rodu Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
P clock division ranges:
te PR Prescaling factor
le 1
so3
Ob 4
SCP1
0
0
1
SCP0
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
1
2
4
8
16
32
64
128
SCR2
0
0
0
0
1
1
1
1
SCR1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
13
1
1
80/139
Doc ID 6996 Rev 5
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