ST72P623 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72P623
STMicroelectronics
ST72P623 Datasheet PDF : 139 Pages
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ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.7 Register Description
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Note: The IDLE bit is not set again until the RDRF
bit has been set itself (that is, a new idle line oc-
curs).
7
0
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
TDRE TC RDRF IDLE OR NF FE PE
being received in the shift register is ready to be
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
Bit 7 = TDRE Transmit data register empty.
register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
t(s) register. An interrupt is generated if the TIE bit = 1
in the SCICR2 register. It is cleared by a software
c sequence (an access to the SCISR register fol-
u lowed by a write to the SCIDR register).
d 0: Data is not transferred to the shift register
ro 1: Data is transferred to the shift register
P Note: Data is not transferred to the shift register
te unless the TDRE bit is cleared.
ole Bit 6 = TC Transmission complete.
s This bit is set by hardware when transmission of a
b frame containing Data is complete. An interrupt is
O generated if TCIE = 1 in the SCICR2 register. It is
- cleared by a software sequence (an access to the
) SCISR register followed by a write to the SCIDR
t(s register).
0: Transmission is not complete
c 1: Transmission is complete
du Note: TC is not set after the transmission of a Pre-
ro amble or a Break.
P Bit 5 = RDRF Received data ready flag.
te This bit is set by hardware when the content of the
le RDR register has been transferred to the SCIDR
o register. An interrupt is generated if RIE = 1 in the
s SCICR2 register. It is cleared by a software se-
b quence (an access to the SCISR register followed
O by a read to the SCIDR register).
access to the SCISR register followed by a read to
the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is
not lost but the shift register is overwritten.
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
0: Data is not received
being transferred causes both frame error and
1: Received data is ready to be read
overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
Doc ID 6996 Rev 5
77/139
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