GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
GS1582-IBE3
Semtech Corporation
GS1582-IBE3 Datasheet PDF : 115 Pages
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4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS1582 is determined by the
input data format. Table 4-1 below lists the possible input signal formats and their
corresponding parallel clock rates. Note that the DVB-ASI input will only be in 10-bit
format, when setting the 20bit/10bit pin LOW.
Table 4-1: Parallel Data Input Format
Control Signals
Input Data Format
DIN [19:10]
DIN [9:0]
PCLK
20bit/ SD/ SMPTE_BYPASS
10bit HD
SMPTE MODE
20-bit DEMULTIPLEXED SD LUMA
10-bit MULTIPLEXED SD
LUMA /
CHROMA
20-bit DEMULTIPLEXED
HD
LUMA
10-bit MULTIPLEXED HD
LUMA /
CHROMA
DVB-ASI MODE
10-bit DVB-ASI
DVB-ASI
DATA
DATA-THROUGH MODE
20-bit SD
10-bit SD
DATA
DATA
20-bit HD
DATA
10-bit HD
DATA
CHROMA
HIGH
IMPEDANCE
CHROMA
HIGH
IMPEDANCE
13.5MHz
27MHz
74.25 or
74.25/
1.001MH
z
148.5 or
148.5/
1.001MH
z
HIGH
LOW
HIGH
HIGH
HIGH LOW
LOW LOW
HIGH
27MHz
IMPEDANCE
LOW
LOW
HIGH
HIGH
DATA
HIGH
IMPEDANCE
DATA
HIGH
IMPEDANCE
13.5MHz
27MHz
74.25 or
74.25/
1.001MH
z
148.5 or
148.5/
1.001MH
z
HIGH
LOW
HIGH
HIGH
HIGH LOW
LOW LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
DVB_ASI
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleanerTM
Data Sheet
40117 - 4
December 2011
28 of 115
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