GS1582-IBE3 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

GS1582-IBE3

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Semtech Corporation 

4.3 SMPTE Mode

The GS1582 operates in SMPTE mode when the SMPTE_BYPASS pin is set HIGH and the

DVB_ASI pin is set LOW.

In this mode, the parallel data will be scrambled according to SMPTE 259M or 292M, and

NRZ-to-NRZI encoded prior to serialization.

4.3.1 HVF Timing

In SMPTE mode, the GS1582 can automatically detect the video standard and generate

all internal timing signals. The total line length, active line length, total number of lines

per field/frame and total active lines per field/frame are calculated for the received

parallel video.

When DETECT_TRS is LOW, the video standard and timing signals are based on the

externally supplied H_Blanking, V_Blanking, and F_Digital signals. These signals go to

the H/HSYNC, V/VSYNC and F/DE pins respectively. When DETECT_TRS is HIGH, the

video standard timing signals will be extracted from the embedded TRS ID words in the

parallel input data. Both 8-bit and 10-bit TRS code words will be identified by the device.

NOTE: IO processing must be enabled for the device to remap 8-bit TRS words to the

corresponding 10-bit value for transmission. See Section 4.9.4.2 for more information.

The GS1582 determines the video standard by timing the horizontal and vertical

reference information supplied at the H/HSYNC, V/VSYNC, and F/DE input pins, or

contained in the TRS ID words of the received video data. Therefore, full

synchronization to the received video standard requires one complete video frame.

Once synchronization has been achieved, the GS1582 will continue to monitor the

received TRS timing or the supplied H, V, and F timing information to maintain

synchronization. GS1582 will lose all timing information immediately following loss of

H, V and F.

The H signal timing should also be configured via the H_CONFIG bit of the internal

IOPROC_DISABLE register as either active line based blanking or TRS based blanking.

See Packet Generation and Insertion on page 69.

Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode,

the H input should be HIGH for the entire horizontal blanking period, including the EAV

and SAV TRS words. This is the default H timing used by the device.

The timing of these signals is shown in Figure 4-2.

GS1582 Multi-Rate Serializer with Cable Driver, Audio

Multiplexer and ClockCleanerTM

Data Sheet

40117 - 4

December 2011

29 of 115

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