T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 32. RGMII AC timing specifications (LVDD = 2.5 V)8 (continued)
Parameter/Condition
Symbol1
Min
Typ
Max
Unit Notes
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT 40
50
60
%
3, 4
Duty cycle for Gigabit
tRGTH/tRGT 45
50
55
%
—
Rise time (20%-80%)
tRGTR
—
—
0.75
ns
5, 6
Fall time (20%-80%)
tRGTF
—
—
0.75
ns
5, 6
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300
ppm.
8. For recommended operating conditions, see Table 3.
9. IEEE specification mandates tSKRGT_TX = ± 0.5 ns. Per erratum A-005177, we see tSKRGT_TX has a wider output skew
range from -0.75 ns to 1.00 ns, which is larger than the specification asks for. If the device cannot cope with this wide skew,
use RGMII at 100 Mbps or 10 Mbps, which allows larger maximum RX skews, or terminate 1000 Mbps RGMII links with
PHYs that accommodate larger RX skews. NOTE: MAC10 is not impacted by erratum A-005177, and it meets industry
specifications.
This figure shows the RGMII AC timing and multiplexing diagrams.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
74
NXP Semiconductors
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