T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

GTX_CLK

output

TXD[7:4][3:0]

output

TX_CTL

output

TXD[3:0]

TXEN

TXD[7:4]

TXERR

tRGTH

tSKRGT_TX

Electrical characteristics

tRGT

tSKRGT_TX

RXD[7:4][3:0]

input

RX_CTL

input

RX_CLK

input

RXD[3:0]

RXD[7:4]

RXDV

RXERR

tSKRGT_RX

tSKRGT_RX

tRGT

tRGTH

Figure 15. RGMII AC timing and multiplexing diagrams

Warning

NXP guarantees timings generated from the MAC. Board

designers must ensure delays needed at the PHY or the MAC.

3.11.3 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces.

Frame Manager's external GE MDIO configures external GE PHYs connected to EMI1

pins. Frame Manager's external 10GE MDIO configures external XFI, XAUI, and HiGig/

HiGig2 PHY connected to EMI2 pins.

The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22 and EMI2

interface timing is compatible with IEEE Std 802.3™ clause 45.

3.11.3.1 Ethernet management interface 1 DC electrical characteristics

The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this

section.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

75

Share Link: