T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 17. DDRCLK DC electrical characteristics3 (continued)
Parameter
Symbol
Min
Typical
Max
Unit
Input current (OVIN= 0 V or OVIN =
IIN
OVDD)
Note:
-50
—
+ 50
μA
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.
Notes
2
3.6.5.2 DDR clock AC timing specifications
This table provides the DDR clock (DDRCLK) AC timing specifications.
Table 18. DDRCLK AC timing specifications5
Parameter/Condition
Symbol
Min
Typ
Max
Unit Notes
DDRCLK frequency
DDRCLK cycle time
DDRCLK duty cycle
DDRCLK slew rate
fDDRCLK
66.7
—
tDDRCLK
5
—
tKHK / tDDRCLK
40
—
—
1
—
133.3
15
60
4
MHz 1, 2
ns
1, 2
%
2
V/ns
3
DDRCLK peak period jitter
—
—
—
± 150
ps
—
DDRCLK jitter phase noise at -56 dBc —
—
—
500
KHz
4
AC Input Swing Limits at 1.8 V OVDD ΔVAC
Notes:
0.35 x OVDD —
0.65 x OVDD V
—
1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD.
4. Phase noise is calculated as FFT of TIE jitter.
5. At recommended operating conditions with OVDD = 1.8V, see Table 3.
3.6.6 Other input clocks
A description of the overall clocking of this device is available in the chip reference
manual in the form of a clock subsystem block diagram. For information about the input
clock requirements of functional modules sourced external of the chip, such as SerDes,
Ethernet management, eSDHC, IFC, see the specific interface section.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
61
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