T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 23. DDR3 and DDR3L SDRAM interface input AC timing specifications4 (continued)

Parameter

Symbol

Min

Max

Unit Notes

Tolerated Skew for MDQS-MDQ/MECC

tDISKEW

—

—

2133 MT/s data rate

-154

154

ps

2, 3

1866 MT/s data rate

-175

175

1600 MT/s data rate

-200

200

1333 MT/s data rate

-250

250

1200 MT/s data rate

-275

275

1066 MT/s data rate

-300

300

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This must be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW = ±(T ÷ 4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

3. 2133 MT/s is only supported for DDR3, not DDR3L.

4. For recommended operating conditions, see Table 3.

This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.

MCK[n]_B

MCK[n]

tMCK

MDQS[n]

MDQ[x]

tDISKEW

tDISKEW

D0

D1

tDISKEW

Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram

3.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing

specifications

This table contains the output AC timing targets for the DDR3 SDRAM interface.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

65

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