T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 21. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1, 7

Parameter

Symbol

Min

Max

4. The voltage regulator for MVREFn must meet the specifications stated in Table 22.

Unit

Note

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

7. For recommended operating conditions, see Table 3.

This table provides the current draw characteristics for MVREFn.

Table 22. Current draw characteristics for MVREFn1

Parameter

Symbol

Min

Current draw for DDR3 SDRAM for MVREFn IMVREFn

—

Current draw for DDR3L SDRAM for

MVREFn

IMVREFn

—

Note:

1. For recommended operating conditions, see Table 3.

Max

500

500

Unit

μA

μA

Notes

—

—

3.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller

interface. The DDR controller supports DDR3 and DDR3L memories. Note that the

required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the

required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

3.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when

interfacing to DDR3 or DDR3L SDRAM.

Table 23. DDR3 and DDR3L SDRAM interface input AC timing specifications4

Parameter

Controller Skew for MDQS-MDQ/MECC

2133 MT/s data rate

1866 MT/s data rate

1600 MT/s data rate

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

Symbol

Min

tCISKEW

—

-80

-93

-112

-125

-142

-170

Max

—

80

93

112

125

142

170

Table continues on the next page...

Unit Notes

ps

1, 3

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

64

NXP Semiconductors

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