Electrical characteristics
Table 27. eSPI AC timing specifications3 (continued)
Characteristic
Symbol 2
Min
Max
Unit
Notes
SPI inputs-Master data (internal clock) input tNIIVKH
3.6
—
setup time
ns
—
SPI inputs-Master data (internal clock) input tNIIXKH
0
hold time
—
ns
—
Clock-high time
Clock-low time
Notes:
tNIKCKH
4
tNIKCKL
4
—
ns
—
ns
—
1. See the chip reference manual for details about the SPMODE register.
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
3. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs
internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
4. n1 and n2 values are -1.0 and 1.0 respectively.
This figure provides the AC test load for the eSPI.
Output
Z0= 50 Ω
RL = 50 Ω
OVDD/2
Figure 12. eSPI AC test load
This figure provides the eSPI clock output timing diagram.
Figure 13. eSPI clock output timing diagram
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
70
NXP Semiconductors