T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
| |||
Electrical characteristics
3.8.1 DDR3 and DDR3L SDRAM interface DC electrical
characteristics
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3 SDRAM.
Table 20. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1, 7
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
Input high voltage
Input low voltage
I/O leakage current
Notes:
MVREFn 0.49 x GVDD
0.51 x GVDD
V
VIH
MVREFn + 0.100 GVDD
V
VIL
GND
MVREFn - 0.100 V
IOZ
-50
50
μA
2, 3, 4
5
5
6
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of GVDD (i.e. ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn - 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specifications stated in Table 22.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
7. For recommended operating conditions, see Table 3.
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3L SDRAM.
Table 21. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1, 7
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
Input high voltage
Input low voltage
I/O leakage current
Notes:
MVREFn 0.49 x GVDD
0.51 x GVDD
V
VIH
MVREFn + 0.090 GVDD
V
VIL
GND
MVREFn - 0.090 V
IOZ
-100
100
μA
2, 3, 4
5
5
6
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of GVDD (i.e. ±13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn - 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
63
Share Link: 