T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 24. DDR3 and DDR3L SDRAM interface output AC timing specifications8
Parameter
Symbol1
Min
Max
Unit Notes
6. Note that for data rates of 1200 MT/s or higher, it is required to program the start value of the DQS adjust for write leveling.
7. 2133 MT/s is only supported for DDR3, not DDR3L.
8. For recommended operating conditions, see Table 3.
NOTE
For the ADDR/CMD setup and hold specifications in Table 24,
it is assumed that the clock control register is set to adjust the
memory clocks by ½ applied cycle for data rates of 1866 MT/s
or less and 9/16 applied cycle for data rates greater than 1866
MT/s. It is recommended that, during system validation,
memory clocks are adjusted to best fit the particular system.
design.
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK
to MDQS skew measurement (tDDKHMH).
MCK[n]_B
MCK[n]
tMCK
tDDKHMH(max)
MDQS
MDQS
tDDKHMH(min)
Figure 10. tDDKHMH timing diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
67
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