T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 24. DDR3 and DDR3L SDRAM interface output AC timing specifications8

Parameter

Symbol1

Min

Max

Unit Notes

MCK[n] cycle time

tMCK

0.938

2

ADDR/CMD output setup with respect to MCK tDDKHAS

—

—

2133 MT/s data rate

0.350

—

ns

2

ns

3, 7

1866 MT/s data rate

0.410

—

1600 MT/s data rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/s data rate

0.744

—

ADDR/CMD output hold with respect to MCK tDDKHAX

—

—

2133 MT/s data rate

0.350

—

ns

3, 7

1866 MT/s data rate

0.390

—

1600 MT/s data rate

0.495

—

1333 MT/s data rate

0.606

—

1200 MT/s data rate

0.675

—

1066 MT/s data rate

0.744

—

MCK to MDQS Skew

> 1600 MT/s data rate

tDDKHMH

—

-0.150

—

0.150

ns

4

4, 6

> 1066 MT/s data rate, ≤ 1600 MT/s data rate

-0.245

0.245

4, 6

MDQ/MECC/MDM output Data eye

tDDKXDEYE

—

—

2133 MT/s data rate

0.320

—

ns

5, 7

1866 MT/s data rate

0.350

—

1600 MT/s data rate

0.400

—

1333 MT/s data rate

0.500

—

1200 MT/s data rate

0.550

—

1066 MT/s data rate

0.600

—

MDQS preamble

tDDKHMP

0.9 x tMCK

—

ns

—

MDQS postamble

tDDKHME

0.4 x tMCK

0.6 x tMCK

ns

—

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD)

from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS

symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are

setup (S) or output valid time.

2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through

control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the

same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two

parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of

the timing modifications enabled by the use of these bits.

5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller

will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

66

NXP Semiconductors

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