T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

3.11.3.3 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC timing specifications.

Table 36. Ethernet management interface 1 AC timing specifications5

Parameter/Condition

Symbol1

Min

Typ

Max

Unit Notes

MDC frequency

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

Notes:

fMDC

tMDCH

tMDKHDX

tMDDVKH

tMDDXKH

—

—

160

—

(5 x tenet_clk) - 3

—

8

—

0

—

2.5

MHz

2

—

ns

—

(5 x tenet_clk) + 3 ns

3, 4

—

ns

—

—

ns

—

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock

frequency of the MgmtClk Clock EC_MDC).

3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods ± 3 ns. For

example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns ± 3 ns.

4. tenet_clk is the Ethernet clock period (Frame Manager clock period).

5. For recommended operating conditions, see Table 3.

3.11.3.4 Ethernet management interface 2 AC electrical characteristics

This table provides the Ethernet management interface 2 AC timing specifications.

Table 37. Ethernet management interface 2 AC timing specifications5

Parameter/Condition

Symbol1

Min

Typ

Max

Unit Notes

MDC frequency

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

Notes:

fMDC

tMDCH

tMDKHDX

tMDDVKH

tMDDXKH

2.5

—

160

—

(5 x tenet_clk) - 3

—

8

—

0

—

—

MHz

2

—

ns

—

(5 x tenet_clk) + 3 ns

3, 4

—

ns

—

—

ns

—

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock

frequency of the MgmtClk Clock EC_MDC).

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

77

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