ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

Preliminary Technical Data

150

100

50

TBD

0

–50

–100

–150

0

0.5

1.0

1.5

2.0

SOURCE VOLTAGE (V)

2.5

3.0

Figure 44. Drive Current F (High VDDEXT)

POWER DISSIPATION

Total power dissipation has two components: one due to inter-

nal circuitry (PINT) and one due to the switching of external

output drivers (PEXT).

See the ADSP-BF51x Blackfin Processor Hardware Reference

Manual for definitions of the various operating modes and for

instructions on how to minimize system power.

Many operating conditions can affect power dissipation. System

designers should refer to (EE-TBD) Estimating Power for

ADSP-BF512/BF514/BF516/BF518(F) Blackfin Processors on the

Analog Devices website (www.analog.com)—use site search on

“EE-TBD.” That document provides detailed information for

optimizing your design for lowest power.

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 45

shows the measurement point for AC measurements (except

output enable/disable). The measurement point VMEAS is VDDEXT/2

or VDDMEM/2 for V /V DDEXT DDMEM (nominal) = 2.5 V/3.3 V.

INPUT

OR

OUTPUT

VMEAS

VM EA S

Figure 45. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Output Enable Time Measurement

Output signals are considered to be enabled when they have

made a transition from a high impedance state to the point

when they start driving.

ADSP-BF512/BF514/BF516/BF518 (F)

The output enable time tENA is the interval from the point when a

reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 46.

tDIS

VOH

(MEASURED)

VOL

(MEASURED)

REFERENCE

SIGNAL

tDIS_MEASURED

tENA

VOH (MEASURED) ؊ ⌬V

VOL (MEASURED) + ⌬V

tDECAY

tENA _MEASURED

VOH(MEASURED)

VTRIP(HIGH)

VTRIP(LOW)

VOL(MEASURED)

tTRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 46. Output Enable/Disable

The time tENA_MEASURED is the interval, from when the reference sig-

nal switches, to when the output voltage reaches VTRIP(high) or

VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for

VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V. Time tTRIP is the interval

from when the output starts driving to when the output reaches

the VTRIP(high) or VTRIP(low) trip voltage.

Time tENA is calculated as shown in the equation:

tENA = tENA_MEASURED – tTRIP

If multiple signals (such as the data bus) are enabled, the mea-

surement value is that of the first signal to start driving.

Output Disable Time Measurement

Output signals are considered to be disabled when they stop

driving, go into a high impedance state, and start to decay from

their output high or low voltage. The output disable time tDIS is

the difference between tDIS_MEASURED and tDECAY as shown on the left

side of Figure 46.

tDIS = tDIS_MEASURED – tDECAY

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load CL and the load current IL. This decay time

can be approximated by the equation:

tDECAY = (CLΔV) ⁄ IL

The time tDECAY is calculated with test loads CL and IL, and with

ΔV equal to 0.5 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V.

The time tDIS_MEASURED is the interval from when the reference sig-

nal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the equation given above. Choose ΔV

to be the difference between the ADSP-

Rev. PrE | Page 51 of 62 | March 2009

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