ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

BF512/BF514/BF516/BF518(F) processor’s output voltage and

the input threshold for the device requiring the hold time. CL is

the total bus capacitance (per data line), and IL is the total leak-

age or three-state current (per data line). The hold time will be

tDECAY plus the various output disable times as specified in the

Timing Specifications on Page 27 (for example tDSDAT for an

SDRAM write cycle as shown in SDRAM Interface Timing on

Page 30).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

30 pF on all pins/balls (see Figure 47). VLOAD is 1.5 V for VDDEXT

(nominal) = 2.5 V/3.3 V. Figure 48 on Page 52 through

Figure 55 on Page 53 show how output rise time varies with

capacitance. The delay and hold specifications given should be

derated by a factor derived from these figures. The graphs in

these figures may not be linear outside the ranges shown.

VLOAD

50:

70:

50:

4pF

2pF

400:

TESTER PIN ELECTRONICS

T1

DUT

OUTPUT

45:

0.5pF

ZO = 50:(impedance)

TD = 4.04 r 1.18 ns

Preliminary Technical Data

TBD

Figure 48. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver A at EVDDMIN

TBD

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 47. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 49. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver A at EVDDMAX

TBD

Figure 50. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver B at EVDDMIN

Rev. PrE | Page 52 of 62 | March 2009

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