ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

Preliminary Technical Data

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 32 and Figure 21 describe SPI port slave operations.

Table 32. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Timing Requirements

tSPICHS

Serial Clock High Period

tSPICLS

Serial Clock Low Period

tSPICLK

Serial Clock Period

tHDS

Last SCK Edge to SPISS Not Asserted

tSPITDS

Sequential Transfer Delay

tSDSCI

SPISS Assertion to First SCK Edge

tSSPID

Data Input Valid to SCK Edge (Data Input Setup)

tHSPID

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tDSOE

tDSDHI

tDDSPID

tHDSPID

SPISS Assertion to Data Out Active

SPISS Deassertion to Data High Impedance

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

ADSP-BF512/BF514/BF516/BF518 (F)

Min

Max

2 × tSCLK –1.5

2 × tSCLK –1.5

4 × tSCLK –1.5

2 × tSCLK –1.5

2 × tSCLK –1.5

2 × tSCLK

1.6

1.6

0

8.5

0

8.5

10

0

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

SPIxSS

(INPUT)

SCKx

(CPOL = 0)

(INPUT)

SCKx

(CPOL = 1)

(INPUT)

tDSOE

MISOx

(OUTPUT)

CPHA=1

MOSIx

(INPUT)

tDSOE

MISOx

(OUTPUT)

CPHA=0

MOSIx

(INPUT)

tSPICHS

tSPICLS

tSPICLK

tHDS

tSPITDS

tSDSCI

tSPICLS

tSPICHS

tDDSPID

MSB

tHDSPID

tDDSPID

tDSDHI

LSB

tSSPID

MSB

VALID

tHSPID

LSB

VALID

MSB

MSB

VALID

tHDSPID

tDDSPID

tHDSPID

LSB

tSSPID

LSB

VALID

tHSPID

Figure 21. Serial Peripheral Interface (SPI) Port—Slave Timing

tDSDHI

Rev. PrE | Page 41 of 62 | March 2009

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